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1. Implementation process of Flow Control
To implement the Flow Control function, we need to have a deep understanding of its control logic units and how each component works together. The following is a detailed analysis of the implementation process of Flow Control:
1. Overview of Flow Control Control Logic Unit Flow Control logic unit mainly includes two parts: the sending end and the receiving end. The sender is responsible for managing and controlling the packets to be sent (TLPs), while the receiver is responsible for receiving and managing incoming data. Sender: Transaction Pending Buffer: Used to store TLPs that are waiting to be transmitted on the same virtual channel (VC). Credits Consumed Counter (CC): Record the total number of credit units occupied by all TLPs in the VC buffer at the sender. Credit Limit Counter (CL): It is determined by the size of the VC buffer on the receiving end, and the receiving end will update the size of CL through Flow Control DLLPs. Flow Control Gathering Logic: Determine whether the receiving end has enough space to receive the next TLP based on CC, CL, and the number of TLPs to be sent. Receiver: Flow Control Buffer: Stores incoming data and header data. Credits Allocated (CrAl): Record the allocated storage space of the VC buffer at the receiving end. Credit Received Counter (CrRcv): Record the total credit units corresponding to all TLPs received by the receiving end.
2. Detailed explanation of the implementation process of Flow Control. In the initial state, we assume that the VC buffer size is 2KB and the credit size of the Non Stored Header is 5DW (20bytes). Therefore, the maximum number of Flow Control units is 2KB/20bytes=102 (decimal)=66 (hexadeci

III. Summary: The implementation process of Flow Control depends on the close cooperation between the sender and receiver. The sender controls the transmission of TLPs by managing CC and judgment formulas, while the receiver updates CL and notifies the sender by managing CrAl and sending Flow Control update DLLPs. This mechanism ensures the smoothness and efficiency of data trans

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